1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a redundancy circuit for remedying an error bit caused during the manufacture of the memory device.
2. Description of the Related Art
When a memory device has some defective memory cells, even if only one, it cannot be delivered as a product. However, due to the existence of debris or the like during the memory chip manufacturing process, it is very difficult to manufacture a chip so that all of its bits operate correctly. As memory micropatterning is advanced, a chip is more and more likely to be adversely affected by such debris and the like.
For this reason, a semiconductor memory employs a redundancy circuit that replaces a defective memory cell with a spare cell to remedy errors ranging from several bits to several kilo bits, thereby maintaining the entire chip as a non-defective article. The redundancy circuit replaces a bit or word line connected to a defective memory cell with a spare bit or word line connected to a spare memory cell provided in the same chip. For example, when bit lines are to be replaced, a spare column decoder having a plurality of fuses for decoding the column addresses of the bit lines is used. The fuses corresponding to the column addresses of the defective memory cell are disconnected. Then, when the addresses of the defective bit lines are input to the decoder, a selection signal is output to spare column selecting lines, thereby selecting spare bit lines. Simultaneously, a signal for selecting bit lines to which the defective memory cell is connected is disabled. As a result, the bit lines are replaced with the spare bit lines. The redundancy circuit for replacing the word lines also uses a spare row decoder having a plurality of fuses for decoding row addresses of the word lines.
In conventional memory devices, columns of memory cells, which are selected by column selection lines, are arranged in units of two (connected to four bit lines) or four (connected to 8 bit lines), for two reasons. First, the column selection lines need to be arranged at short intervals since the memory device has many small memory cells, thus having a large storage capacity. Second, it is necessary to reduce the bits of a column address by one bit, thereby to decrease the area occupied by the column decoder.
In a conventional redundancy circuit, the number of memory-cell columns, which are selected by one spare column selection line, is equal to the number of the columns which are selected by one column selection line. Hence, a spare column selection line can be substituted only for a column selection line which has a predetermined number of bit lines. Most conventional devices have only one spare column line. If they have two or more spare column lines, they would have more spare memory cells, and would inevitably have a larger chip size.
The probability D that short-circuiting between any adjacent two bit lines in the conventional circuit described above cannot be remedied, is given by the following equation. ##EQU1##
where Nsbl: the number of spare bit lines
Nbl: the total number of bit lines excluding spare bit lines
For example, when the number of spare bit lines Nsbl is 4 and the total number of lines excluding spare bit lines Nbl is 8, .beta.=1/7. Namely, when each memory chip has one short-circuited portion, one out of every seven memory chips is estimated to be incapable of being remedied. In order to remedy such inter-bit line short-circuiting, a large number of spare column decoders must be provided, resulting in the increase in spare memory cells and considerable increase in chip area. Manufacturing cost also augments.